Optimization of Direct Tunneling Gate Leakage Current in Ultrathin Gate Oxide FET with High-K Dielectrics
نویسندگان
چکیده
This paper presents the impact of parameter optimization of n-type MOSFET for direct tunneling gate current using ultrathin Si3N4 and HfO2 with EOT (Equivalent Oxide Thickness) of 1.0 nm. This work is compared with TCAD santaurus simulation results to verify that accuracy of the model and excellent reduction in gate leakage with the introduction of the high-k gate dielectrics (HfO2 & Si3N4) in place of SiO2. It also observed that highk based MOSFET exhibits improved performance of Subthreshold Swing, Ion, Ioff Ion/Ioff ratio and transconductance.
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